Double Data Rate (DDR and DDRII) and Quad Data Rate (QDR and QDRII) are industry standard architectures for high-speed networking Static Random Access Memory (SRAM). The DDR architecture doubles the data rate of standard SRAM by performing two memory accesses per clock cycle. In the QDR architecture, the input port and the output port are separate and operate independently allowing two memory reads and two memory writes per clock cycle. With two memory reads and writes per clock cycle, the QDR architecture quadruples the data rate of standard SRAM by allowing four memory accesses per clock cycle.
The QDR architecture was originally designed for high speed SRAM interfaces. However, the QDR architecture has been adopted for other high frequency applications, for example, as a standard interface to memory based co-processors.
The QDR architecture defines a master clock pair that is used to control read and write accesses to the SRAM. For example, all data read from SRAM is aligned to the rising edges of the master clock pair.
When operating at a low operating frequency, for example, below 133 MHz, there is sufficient time for a bus master such as, an ASIC or a microprocessor coupled to the QDR device to use the rising edges of the master clock pair to capture the data synchronized to the master clock pair. However, as the operating frequency of the QDR device is increased, data valid windows and hold times decrease accordingly. Data synchronized to the master clock pair by the memory based co-processor may not be valid when captured by the bus master using the master clock pair. In order to allow the bus master to capture valid data when operating at higher frequencies, the QDR architecture also defines a data clock pair. The data clock pair is a phase-shifted version of the master clock pair.
The QDR architecture permits the bus master to use the data clock pair to capture the data instead of the master clock pair in order to meet data setup and hold times at the bus master. Thus, the memory-based co-processor must synchronize the data to the data clock pair after it has been read from data storage. There can be a significant phase difference (skew) between the master clock pair and the data clock pair.